An EPROM (Electrically Programmable Read Only Memory) with a floating gate structure is well-known as an electrically writable nonvolatile memory. The EPROM is structured in such a way that a channel region is provided between source and drain regions on a semiconductor substrate. A first insulating film is formed on the channel region, and a floating gate electrode is formed on the first insulating film. A second insulating film is formed on the floating gate electrode, and a control gate electrode is formed on the second insulating film.
The EPROM performs write operations by applying a high voltage to the drain region and control gate electrode to generate hot electrons in the channel region near the drain of the semiconductor substrate. The EPROM then injects these hot electrons into the floating gate electrode with acceleration.
The EPROM performs read operations by applying an operating voltage to the area between the source and drain regions and the control gate electrode so as to detect the level of current flowing between the source and drain regions.
In general, stored data in an EPROM can be erased by applying ultraviolet rays. Recently, however, EPROMs that can electrically erase the stored data have been widely used. In these EPROMs, the thickness of the first insulating film is reduced, and electrons are discharged through the thin insulating film from the floating gate electrode to the source region, the drain region or the channel region by a tunneling phenomenon so that the stored data can be erased electrically.
In addition, a recent proposal would use an independent erasing gate electrode to erase data from a memory cell structure (see U.S. Pat. No. 5,070,032). Under this arrangement, a tunnel insulating film is formed as a tunneling medium between the erasing gate electrode and the floating gate electrode. An erase voltage is applied to the erasing gate electrode and electrons are tunneled from the floating gate electrode to the erasing gate electrode so that the data is erased. A semiconductor memory which uses the erasing gate electrode is generally referred to as a "flash memory" because all memory cells, or memory cell groups for every block are erased at the same time.
FIG. 8 is a plan view and FIGS. 9(a) and 9(b) are sectional views showing a floating gate type semiconductor memory with an erasing gate according to the prior art. FIG. 9(a) is a sectional view taken along the line A-A' shown in FIG. 8. FIG. 9(b) is a sectional view taken along the line B-B' shown in FIG. 8. In FIGS. 8, 9(a) and 9(b), a semiconductor substrate is indicated at 1, a source region is indicated at 2, a drain region is indicated at 3, a gate insulating film is indicated at 4, a floating gate electrode is indicated at 5, a layer insulating film is indicated at 6, a control gate electrode is indicated at 7, a silicon oxide film used for element isolation is indicated at 8 and 9, an erasing gate electrode is indicated at 10, a tunnel insulating film is indicated at 11, and a silicon oxide film for electrically insulating the erasing gate electrode 10 from the floating gate electrode 5 is indicated at 12 and 13.
The structure of a tunnel region formed between the erasing gate electrode and the floating gate electrode in the floating gate type semiconductor memory comprising the erasing gate according to the prior art shown in FIG. 9, and a method for manufacturing the floating gate type semiconductor memory will be described below.
As shown in FIG. 10, a predetermined portion of the silicon oxide film 8 formed on the semiconductor substrate 1 by the known chemical vapor deposition method is selectively etched. Then, a side wall film made of the silicon oxide film 9 is formed on the side wall of the silicon oxide film 8 by the known chemical vapor deposition method and the anisotropic dry etching technique. Thereafter, the silicon oxide film 4 which acts as a gate insulating film is formed by the thermal oxidation method. Subsequently, a polysilicon film 5, a silicon oxide film 6, a polysilicon film 7, and a silicon oxide film 13 are sequentially laminated over the whole face. The polysilicon films 5 and 7 and the silicon oxide film 13 are formed by a known chemical vapor deposition method. The silicon oxide film 6 is formed by thermally oxidizing the polysilicon film 5.
As shown in FIG. 11, the polysilicon film 7 and the silicon oxide film 13 are selectively etched by a known photoetching technique using a photoresist. Thus, a control gate electrode made of the polysilicon film 7 is formed. Then, a first side wall film made of the silicon oxide film 12 to which impurities are not added and a second side wall film made of a silicon oxide film 14 to which phosphorus or boron is added as impurities are formed on the side walls of the silicon oxide film 13 and the polysilicon film 7 by the known chemical vapor deposition method and the anisotropic dry etching technique. Thus, a double side wall structure is formed.
As shown in FIG. 12, the polysilicon film 5 is etched by using the second side wall film as a mask. Consequently, a floating gate electrode made of the polysilicon film 5 is formed.
As shown in FIG. 13, the second side wall film made of the silicon oxide film 14 is removed by the known wet etching method. In this case, the first side wall film to which the impurities are not added is etched at a speed of 1/50 to 1/100 of that of the silicon oxide film to which the impurities are added. For this reason, the first side wall film is hardly etched. At the wet etching step, a part of the upper face and the side wall of the floating gate electrode are exposed. The exposed portion acts as a tunneling region. Then, the exposed portion is thermally oxidized to form the tunnel insulating film 11. Finally, the erasing gate electrode made of the polysilicon film 10 is formed on the tunnel insulating film 11.
According to the structure of the floating gate type semiconductor memory comprising the erasing gate electrode according to the prior art and the method for manufacturing the floating gate type semiconductor memory, however, the tunneling region is positioned on the exposed portions of a part of the upper face and the side wall of the floating gate electrode. For this reason, the double side wall structure has to be used. Consequently, it is very hard to perform control during manufacture. Thus, there are problems in respect of stability during manufacture. In addition, it is necessary to use, as the second side wall film, the silicon oxide film to which the impurities are added. Usually, the growth of the silicon oxide film to which the impurities are added causes the generation of particles easily. Therefore, there is a possibility that the yield is deteriorated and the reliability is damaged.